The invention relates to an integrated circuit comprising a substrate with an electrically insulating surface, on which surface are present:
an insulating layer;
a semiconducting layer which is at least substantially unpatterned;
a first patterned layer comprising a pattern of electrodes and other electrical conductors; and
a second patterned layer which comprises a pattern of electrical conductors and which is separated from the first patterned layer and from the semiconducting layer by the insulating layer,
wherein the first patterned layer is in contact with the semiconducting layer and comprises a first and a second transistor, said transistors each having a first and a second electrode, of which electrodes at least the first electrodes comprise a number of electrically conducting tracks which are at least substantially parallel.
Such an integrated circuit, also referred to as IC, is known from D. M. de Leeuw et al., IEDM 97, 331-336. This integrated circuit is manufactured from a polymeric material and comprises combinations of field effect transistors in 2-input NAND gates and inverters. The patterned layers are manufactured from polyaniline and have electrically insulating and electrically conducting portions. The first electrode is a source electrode and the second electrode a drain electrode, or the other way round. The first and second electrodes are interdigitated: the parallel tracks of each of the electrodes lie alongside those of the other like the teeth of two forks.
A disadvantage of this circuit is the occurrence of leakage currents between transistors through the unpatterned semiconducting layer. These leakage currents hamper the independent functioning of the transistors and thus cause an interference in input and output signals of the circuit.
It is an object of the invention to provide an integrated circuit of the kind described in the opening paragraph in which the occurrence of leakage currents between transistors through the semiconducting layer is counteracted.
According to the invention, this object is achieved in that the first electrode of the first transistor and the first electrode of the second transistor both perform the same function of source and drain electrode; the circuit comprises means for giving the first electrode of the first transistor and the first electrode of the second transistor in the first patterned layer the same potential in operational condition; and the first patterned layer between the first and the second transistor is free from any electrical conductor which has a potential other than that of the first electrode of the first transistor in the operational condition.
Since the first electrodes of two transistors situated next to one another have the same potential, there is no driving force for a displacement of charge from the first electrode, for example in the first transistor, to an electrical conductor outside the first transistor. Leakage currents through the semiconducting layer are prevented thereby. An advantage of the circuit according to the invention is the fact that it is not necessary to pattern the semiconducting layer. The omission of an additional, lithographic patterning step constitutes a saving in production cost.
Reduction of leakage current between the first and the second transistor is especially important, if said transistors are part of different functional blocks. Such blocks are for example NAND- or NOR-blocks, or are blocks relating to different memory units. It is common practice in the design of integrated circuits, that neighboring blocks do not need to be related functionally. Hence, leakage current from the first transistor in a first block to the second transistor in a second blockxe2x80x94in an integrated circuit according to the prior artxe2x80x94will introduce noise in the output of the second block. This noise is completely unrelated to any signal in the block itself, and will probably be a severe cause of malfunctioning of the integrated circuit. In the integrated circuit of the invention said leakage currentxe2x80x94and hence said noisexe2x80x94is prevented and the signal-to-noise ratio is substantially improved.
Examples of transistors are field effect and bipolar transistors. Field effect transistors may be constructed in a thin-film shape, referred to as TFT, in the shape of a conductor-insulator-semiconductor structure, referred to as MISFET, and in the shape of a conductor-semiconductor structure, referred to as MESFET. Transistors may be used as switches and as components in a memory element.
The substrate material used may for example be silicon, quartz, glass, a ceramic material, or a polymer such as polyimide. Preferably, the substrate material is polyimide. The patterned layers preferably comprise organic polymeric material, but they may also comprise metal or inorganic conductors such as gold, silver, or doped silicon, either as the main component or in the form of a thin layer on an organic polymer material. The semiconducting layer comprises, for example, doped silicon or an organic material which is suitable as a semiconductor. The thickness of the semiconducting layer lies between approximately 5 nm and a few micrometers. The insulating layer comprises, for example, a material such as SiO2, Si3N4, polyvinyl phenol, polyvinyl alcohol, or cyanoethyl pullane.
In an embodiment of the IC according to the invention, said means are an electrical conductor in the first patterned layer which interconnects the first electrodes of the first and the second transistor. Such an electrical conductor is an interconnect line. The interconnect line may connect a plurality of first electrodes in transistors to one another. Furthermore, the interconnect line may be at the same time a supply line which applies the so-called supply voltage. An alternative means is formed by an interconnect line between said first electrodes in an additional patterned layer, which interconnect line is in contact with the first patterned layer but not with the semiconducting layer. Such an interconnect line may also be separately provided.
A further embodiment is characterized in that the first electrode and the second electrode of the first transistor are interdigitated and together form a pair, which pair has a number of at least substantially parallel electrically conducting tracks; two outermost tracks of the interdigitated pair belonging to the first electrode. The second electrode is not connected to an electrode in the second transistor because of the desired independence of the first and the second transistor and the mutual interconnection of the first electrodes of these transistors. To prevent potential differences, and accordingly leakage currents, the second electrode is screened off from the electrodes in the second transistor. This screening takes place by means of conductive tracks of the first electrode, which tracks lie at an outer side of the interdigitated electrode pair. An outer side is meant to be a side here in the patterned layer where none of the electrodes of the pair is connected to another electrical conductor. A track at an outer side is an outermost track. It is possible to integrate neighboring outermost tracks in the first electrodes of the first and the second transistor into one track. An outermost track may alternatively be branched or split.
In a special embodiment of this circuit, the first electrode has at least three tracks, of which two outermost tracks are the longest. The lengthened shape optimally screens off the outermost tracks of the second electrode and the other electrical conductors connected thereto from the adjoining transistors.
In a further embodiment of the IC according to the invention, the conductor interconnecting the first electrodes is a first supply line; the first and the second transistor form part of a first NAND function block, which NAND function block in addition comprises a third transistor; the NAND function block comprises an interdigitated pair of a source and a drain electrode of the third transistor in the first patterned layer, of which pair a first electrode is connected to a second supply line, such that the NAND function block lies between the first and the second supply line in as far as this block is present in the first patterned layer; and the second supply line interconnects the first electrode of the third transistor and a first electrode of a second NAND function block. The operation of a NAND function block is known to those skilled in the art of semiconductor manufacture. One of the two supply lines has a supply voltage greater than zero, while the other one is connected to ground. This embodiment of the IC has the advantage that the NAND function block can be accommodated in a simple manner in a row of NAND function blocks. Such a row is eminently suitable for use in a memory for data storage.
In a further embodiment of the IC according to the invention, the electrical conductor which transfers signals chosen from the group of input signals and output signals to the first transistor is present in the second patterned layer. A conductor having such a function is known to those skilled in the art as signal wire. At least one signal wire is present for each transistor. Since the second patterned layer does not make contact with the at least substantially unpatterned semiconducting layer, no leakage current will flow from a signal wire to any other electrical conductor through the semiconducting layer in this embodiment. It is advantageous in the case where NAND function blocks are present in the IC when signal wires of the IC are present in the second patterned layer at the areas of the NAND function blocks. Portions of the first patterned layer may thus be kept free from electrical conductors between two transistors. If the signal wires transmitting the input or output signal to a transistor all lie in the second patterned layer, it is necessary for at least one of these signal wires to be connected to an electrical conductor in the first patterned layer. A via or vertical interconnect area achieves such a connection. To obtain a minimum contact resistance, it is favorable when the IC is given a bottom gate structure. In this structure, the second patterned layer lies first on the substrate, then the insulator, then the second patterned layer, and finally the semiconducting layer.
In another embodiment of the IC according to the invention, an auxiliary conductor in contact with one of the supply lines lies between a first and a second electrical conductor in the first patterned layer, the latter two conductors being situated outside a transistor. The auxiliary conductor acts as a leakage current trap. Normally, a leakage current would occur between the first and the second electrical conductor through the unpatterned semiconducting layer, which would affect the transmission of signals in the conductors in an uncontrolled manner. In this embodiment of the IC according to the invention, by contrast, two leakage currents occur which are both branched off to a supply line having a constant supply voltage. The two leakage currentsxe2x80x94one leakage current between the first conductor and the auxiliary conductor and another leakage current between the second conductor and the auxiliary conductorxe2x80x94thus influence said signal transmission in a controlled manner or not at all. The first and the second conductor are, for example, signal wires which couple the input and supply signals of a number of transistors. Preferably, these conductors are present at a side of a supply line which is free from transistors.
In a further embodiment of the IC according to the invention, at least one patterned layer is constructed so as to have a relief structure. This embodiment prevents leakage currents between conductors in the patterned layer through the insulating portions of this layer. Preferably, both patterned layers are constructed as relief structures. Relief structures of polymeric material are known per se from WO-A 99/10939. When relief structures of polyaniline as the polymeric material are used, the conductivity of the relief structures is enhanced in that the polyaniline is doped for a second time. Preferably, the pattern in the structure comprises electrical conductors and recesses which are less than 10 xcexcm wide. Such minute dimensions enhance the characteristics of a transistor, especially as regards the on/off ratio.
In an embodiment of the IC according to the invention, the semiconducting layer mainly comprises organic material. In a further embodiment of the IC according to the invention, at least one patterned layer comprises mainly organic polymeric material. An integrated circuit manufactured from polymeric materials has the advantage inter alia of being inexpensive. In addition, the circuit has a high flexibility in dependence on the substrate material.
Examples of organic materials which can be used for the semiconducting material are polythienylene-vinylene, polythiophene, polyphenylene-vinylene, polyfuranylene-vinylene, polypyrrole, polyphenylene, polyacetylene, polyfurane, and polyaniline. Substituted variants of these polymeric materials may also be used. Examples of substituents are alkyl and alkoxy groups and groups having a ring structure such as alkylenedioxy groups. Such groups are preferably C1 to C10-alkyl, -alkoxy, or -alkylene.
Doped forms of various polymeric materials are known as electrically conducting materials. Examples of such materials are polyaniline, polyimide, polythiophene, polypyrrole, poly(p-phenylenesulfide) and copolymers of these materials. Other materials which may be used are the substituted variants of these materials. Examples of substituents are alkyl, alkoxy, and alkylalkoxy groups. Examples are in particular poly-3-alkylthiophenes, poly-3,4-dialkoxythiophenes, poly-3,4-alkylthiophenes, and poly-3,4-alkylenedioxythiophenes, and furthermore other polythiophenes with ring-shaped substituents as known from U.S. Pat. No. 4,959,430 and EP-A 628 560. Such substituted groups are preferably C1 to C10-alkyl, -alkoxy, or -alkylenedioxy.